PROTO-8 Frequently Asked Questions

Listed below are questions frequently asked by our customers regarding this product. Every attempt is made to provide the latest information, however, all information is subject to change over time. When in doubt or if your question can not be answered here please contact SCIDYNE directly.

What PC/104 Bus signals are available on a PROTO-8?
The PROTO-8 enables easy access to all the PC/104 8-bit (J1/P1) signals, including a buffered data bus and decoded I/O chip selects. An optional adapter (P8-16 Model #100-7578) is available to gain access to all the PC/104 16-bit (J2/P2) signals. A user is free to create their own decoding circuits or use the default decoding built on the PROTO-8. The decoding logic is based on a simple address comparator and single pre-programmed GAL16V8. It provides four chip selects across 16-bytes beginning from the user defined PROTO-8 base address. These signals are normally HIGH (logic "1") and go LOW (logic "0") when the HOST emits an address within their respective range. Two of the signals (Y2* and Y3*) are further qualified and will only be activated in conjunction with the hosts IOR* and IOW* signals respectively. In addition to the default  signals, the GAL also offers six undefined user accessible signals.  Because the decoding logic is contained in a GAL, the user is free to reprogram the device and customize the logic as needed.

NOTE: The user must have logic compiler software and a hardware programmer in order to change the GAL logic. These items are not supplied with the PROTO-8.

PROTO-8 I/O Decoded Signals
Name	Active Range (Offset from Base)	Description
Y0*	0x000 - 0x003	These two signals are normally high and go low whenever the PC/104  address lines match the range of the decoded address. This includes I/O, MEMORY, DMA and REFRESH operations. They are intended to be connected to bi-directional peripheral chips which have separate IOR* and IOW* inputs (82C55, 82C54 or similar). However, they can also be used with external logic (typically an OR gate) to create additional chip selects which are only activated during INPUT or OUTPUT operations.
Y1*	0x004 - 0x007
Y2*	0x008 - 0x00B	This signal is normally high and goes low when the PC/104 address lines match the range of the decoded address AND the host is performing a I/O write (OUTPUT) operation.  This signal is most often used to drive the clock input of output only devices such as octal latches and flip/flops ('273, '274 or similar).
Y3*	0x00C - 0x00F	This signal is normally high and goes low when the PC/104 address lines match the range of the decoded address AND the host is performing a I/O read (INPUT) operation.  This signal is most often used as the enable of input only devices such as octal buffers ('244 or similar).